`timescale 1ns / 1ps
`include "def.v"

module D_GRF(
    input [31:0] PC,
    input [4:0] RdReg1,
    input [4:0] RdReg2,
    input [4:0] WrReg,
    input [31:0] WD,
    input clk,
    input reset,
    output [31:0] RD1,
    output [31:0] RD2
    );

    reg[31:0] regfile[0:31];
    integer i;

    initial begin
        for(i=0; i<32; i=i+1) regfile[i] = 32'h0;
    end

    always @(posedge clk) begin
        if(reset) begin
            for(i=0; i<32; i=i+1) regfile[i] <= 32'h0;
        end 
        else begin
            regfile[WrReg] <= (WrReg != 5'h0) ? WD : 32'h0;
        end
    end

    // 接收数据前递
    assign RD1 = (RdReg1 == 5'h0) ? 32'h0 :
                 (WrReg == RdReg1 && RdReg1 != 5'h0) ? WD : 
                 regfile[RdReg1];
    assign RD2 = (RdReg2 == 5'h0) ? 32'h0 :
                 (WrReg == RdReg2 && RdReg2 != 5'h0) ? WD : 
                 regfile[RdReg2];

endmodule
